Multiplication device and sum of products calculation device

ABSTRACT

In the first half of one cycle of a clock, a partial product generation circuit of each stage in a multiplication array generates partial products on the basis of one bit of the 16 low-order bits of multiplier data and the bits of multiplicand data. An accumulative addition circuit of each stage in the multiplication array accumulatively adds an initial value or an output from a previous accumulative addition circuit to the partial products to perform half necessary multiplication, writes the accumulative result in a latch as intermediate result data, and writes the predetermined number of bits of an output from the accumulative addition circuit of each stage at a predetermined bit position of the latch. In the second half of the clock, the partial product generation circuit of each stage generates partial products on the basis of one bit of an output from a latch holding the 16 high-order bits of a multiplier and the bits of the multiplicand data. In addition, the accumulative addition circuit of each stage accumulatively adds the intermediate result data or an output from a previous accumulative addition circuit to the partial products to perform the remaining half the calculation, and writes the final accumulative addition result and the predetermined number of bits of the output from the accumulative addition circuit of each stage in a latch.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multiplication device and a sum ofproducts calculation device which are used as calculation devices suchas a data processor and a microprocessor.

2. Prior Art

As a technique in the field of this type, the technique shown in FIGS. 1to 4 is available.

FIG. 1 is a view showing the arrangement of a conventionalmultiplication device using a carry save adder scheme.

This multiplication device has a function of performing multiplicationof 8 bits×8 bits. More specifically, multiplication between 8-bitmultiplicand data X<0:7> and 8-bit multiplier data Y<0:7> is performed,thereby outputting a multiplication result OUT<0:15>.

As shown in FIG. 1, this multiplication device is constituted by an8-bit multiplicand register 101 for holding a multiplicand X, an 8-bitmultiplier register 102 for holding a multiplier Y, and a multiplicationunit 103.

The multiplication unit 103 is constituted by eight multiplicationarrays 104 and a carry look ahead adder 105 connected to the lastmultiplication array. Each of the multiplication arrays 104 comprises apartial product generation circuit constituted by eight AND gates 104afor generating partial products and an accumulative addition circuitconstituted by eight full adders 104b for accumulatively adding thegenerated partial products.

In this case, the truth table of outputs Z and CO with respect to inputsA, B, and C of each full adder 104b is shown in FIG. 2.

The operation of this multiplication device will be described below.

In the first multiplication array 104, a logical AND between an outputX<0:7> from the multiplicand register 101 and an output Y<7> from themultiplier register 102 is calculated, and an output from the firstmultiplication array 104 is added to the second multiplication array104. In the second multiplication array 104, partial products areaccumulatively added by using the output from the first multiplicationarray 104, the output X<0:7> from the multiplicand register 101 and theoutput Y<6> from the multiplier register 102.

Similarly, accumulative additions are sequentially performed by thethird to eighth multiplication arrays 104. Finally, the carry look aheadadder 105 performs a carry look ahead addition to an output from theeighth multiplication array. As a result, outputs from the carry lookahead adder 105 are generated as multiplication results OUT<0:7>, andoutputs from the full adders 104b located at the least significant bitsof the first to eighth multiplication arrays are generated asmultiplication results OUT<9:15>.

FIG. 3 is a view showing the arrangement of a conventional sum ofproducts calculation device using a carry save adder scheme.

This sum of products calculation device has a function of performing sumof products calculation of 8 bits×8 bits+16 bits. That is, the productbetween 8-bit multiplicand data X<7:0> and 8-bit multiplier data Y<7:0>is calculated, and a 16-bit addition is performed, thereby outputtingsum of products results OUT<15:0>.

This sum of products calculation device comprises, as shown in FIG. 3,an 8-bit multiplicand register 111 for holding the multiplicand X, an8-bit multiplier register 112 for holding the multiplier Y, and amultiplication unit 113.

The multiplication unit 113 is constituted by eight multiplicationarrays 114 to which the output sides of a multiplicand register 111 anda multiplier register 112 are connected, a multiplication resultregisters 115, 118 connected to the last multiplication array 114, and acarry look ahead adder (adder with CLA) 116.

Each of the multiplication arrays 114 comprises a partial productgeneration circuit constituted by eight multiplication arrays 114a forgenerating partial products and an accumulative addition circuitconstituted by eight full adders 114b for accumulatively adding thegenerated partial products. In addition, the multiplication resultregister 115 is a 16-bit register for holding an accumulative additionresult set in a carry save form (state divided into carry and sumstates). The multiplication result register 118 is a register forholding the OUT<6:0> from the full adders 104b located at the leastsignificant bits of the first to eighth multiplication arrays. The carrylook ahead adder 116 is a carry look ahead adder (8 bits+8 bits) forreturning the carry save from of the accumulative addition result to ageneral form.

A carry look ahead adder 117 (16 bits+16 bits) for adding themultiplication result to sum of products data is connected to the outputof the multiplication device 113.

According to the sum of products calculation device arranged asdescribed above, the first multiplication array 114 generates partialproducts on the basis of all bits of the multiplicand and the leastsignificant bit <0> of the multiplier, the second multiplication array114 generates partial products on the basis of the second bit<1> fromthe least significant bit of the multiplier and all bits of themultiplicand, and the accumulative addition between the partial productsgenerated by the second multiplication array 114 and the partialproducts generated by the first multiplication array 114 is performed.Similarly, generation of partial products and an accumulative additionare repeated in the third to eighth multiplication arrays 114, themultiplication results between the multiplicands and the multipliers areobtained in a carry save form (the same operation as that of themultiplication device shown in FIG. 1).

After the multiplication results are temporarily stored in themultiplication result registers 115, 118, the multiplication results areadded to each other by the carry look ahead adder 116, thereby obtaininga 16-bit multiplication result. Thereafter, the carry look ahead adder117 performs addition for the multiplication result again to add sum ofproducts data <15:0> to the multiplication result, thereby obtaining asum of products calculation result OUT<15:0>.

FIG. 4 is a view showing the arrangement of a conventionalmultiplication device using a repeat addition scheme.

The multiplication device has a function of performing multiplication of32 bits×32 bits. That is, multiplication between 32-bit multiplicanddata X<0:31> and 32-bit multiplier data Y<0:31> is performed.

As shown in FIG. 4, this multiplication device comprises a 32-bitmultiplicand register 121 for holding multiplicand data X, a 32-bitmultiplier register 122 for holding multiplier data Y, a 32-bit register123 for holding an accumulative addition result obtained in the middleof multiplication, a 32-bit adder 124 for adding the contents of themultiplicand register 121 to the contents of the register 123, and aselector 125 for selecting and outputting an output ADD<0:31> from theadder 124 when a least significant bit Y<31> of the multiplier register122 is "1", and selecting and outputting an output Z<0:31> from theregister 123 when the least significant bit Y<31> is "0". Note that themultiplication result is finally stored in the multiplier register 122.

An output SEL<0:30> from the selector 125 is written in Z<1:31> of theregister 123 the moment a carry output CARRY from the adder 124 iswritten in a most significant bit Z<0> of the register 123, a leastsignificant bit SEL<31> of an output from the selector 125 is written ina most significant bit Y<0> of the multiplier register 122, and Y<0:30>of the multiplier register 122 is written in Y<1:31> of the multiplierregister 122. The above series of processes are repeated 32 times.

More specifically, as one process unit, a process in which, according toa value Y<i> (i=0 to 31) of each digit of the multiplier Y, themultiplicand X<0:31> is added to the register 123 for holding theaccumulative addition result while the multiplicand X<0:31> is shiftedright by one bit (when Y<i>=1) or the contents of the register 123 areonly shifted right by one bit without adding the multiplicandX<0:31>(when Y<i>=0); and a process in which the ith bit from the mostsignificant bit of the multiplication result fixed in the ith process isstored in the most significant bit of the multiplier register 122 whilethe multiplier register 122 is shifted right by one bit are performed.When this process unit is repeated 32 times (i=0 to 31), the low-order32 bits of the multiplication result are stored in the multiplierregister 122, and the upper 32 bits are stored in the register 123.

However, in the prior art, the following problems are posed.

(1) Since calculation is performed in units of clocks, all hardwarerequired for one clock must be equipped, and a circuit areadisadvantageously increases. That is, in the examples shown in FIGS. 1and 3, partial product generation circuits and accumulative additioncircuits which are used to calculate partial products are required. Forthis reason, in calculation of 32 bits×32 its, 32×32=1,024 full addersand 32×32=1,024 partial product generation circuits are required,thereby disadvantageously increase a circuit formation area.

(2) In the example in FIG. 4, the number of required parts isconsiderably smaller than that in the example shown in FIG. 1. However,addition is repeated times number of which is equal to the number ofbits of multiplication. For this reason, as a bit width increases, acalculation time becomes enormous, and high-performance calculationcannot be performed.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the abovecircumstances, and has as its object to a multiplication device and asum of products calculation device in which an amount of hardware isreduced without increasing a calculation process time.

It is another object of the present invention to provide amultiplication device and a sum of products calculation device capableof reducing a circuit area.

In order to achieve the above object, the present invention provides amultiplication device, comprising: a multiplicand holding circuit forholding multiplicand data; a multiplier holding circuit for holding thepredetermined number of bits from high-order bits of multiplier data; afirst selector for switching the predetermined number of bits fromlow-order bits of multiplier data to an output from said multiplierholding circuit according to turning from the first or second half of aclock to the second or first half of the clock; an intermediate resultholding circuit for holding intermediate result data; a second selectorfor switching an initial value to an output from said intermediateresult holding circuit according to turning from the first or secondhalf of the clock to the second or first half of the clock; a pluralityof partial product generation circuits for generating partial productson the basis of an output from said first selector and an output fromsaid multiplicand holding circuit; a plurality of accumulative additioncircuits for performing accumulative addition on the basis of an outputfrom said second selector or an output from a previous accumulativeaddition circuit and outputs from said partial product generationcircuits to generate the intermediate result data serving as anintermediate result of multiplication; an accumulative addition resultholding circuit for holding an output from the predetermined number ofsaid accumulative addition circuits and some of outputs from saidaccumulative addition circuits; and an output holding circuit forstoring some of the outputs from said accumulative addition circuits,characterized in that,

at a first timing which is the first or second half of the clock,

said first selector selects the predetermined number of bits from thelow-order bits of the multiplier data, said second selector selects theinitial value, each partial product generation circuit generates partialproducts on the basis of one bit of an output from said first selectorand an output from each bit of said multiplicand holding circuit, eachaccumulative addition circuit adds an output from said second selectoror an output from a previous accumulative addition circuit to an outputfrom said partial product generation circuit, writes an output from thepredetermined number of said accumulative addition circuits in saidintermediate result holding circuit as the intermediate result data, andwrites the predetermined number of bits of the output from eachaccumulative addition circuit at a predetermined bit position of saidoutput holding circuit;

at a second timing which is the second or first half of a clock afterthe clock switches,

said first selector selects an output from said multiplier holdingcircuit, said second selector selects an output from said intermediateresult holding circuit, each partial product generation circuitgenerates partial products on the basis of one bit of the output fromsaid first selector and an output from each bit of said multiplicandholding circuit, each accumulative addition circuit adds an output fromsaid second selector or an output from a previous accumulative additioncircuit to an output from said partial product generation circuit, andwrites the output from said predetermined accumulative addition circuitand the predetermined number of bits of the output from eachaccumulative addition circuit in said accumulative addition resultholding circuit.

More specifically, according to the multiplication device of thisinvention, at the first timing which is the first or second half of theclock, each partial product generation circuit generates partialproducts on the basis of one bit of the low-order bits of the multiplierdata and bits of the multiplicand data, each accumulative additioncircuit accumulatively adds the initial value or an output from theprevious accumulative addition circuit to the partial products toperform calculation which is half necessary multiplication, writes theaccumulation result in the intermediate result holding circuit asintermediate result data, and writes the predetermined number of bits ofan output from each accumulative addition circuit at a predetermined bitposition of the output holding circuit. At the second timing at whichthe clock is switched to another one, each partial product generationcircuit generates partial products on the basis of one bit of an outputfrom the multiplier holding circuit and bits of the multiplicand data,each accumulative addition circuit accumulatively adds the intermediateresult data or an output from the previous accumulative addition circuitto the partial products to perform the remaining half the calculation,and writes the accumulative addition result from said predeterminedaccumulation addition circuit and the predetermined number of bits of anoutput from each accumulative addition circuit in the accumulativeaddition result holding circuit.

Therefore, according to the multiplication device of this invention, amultiplication device having a small circuit scale and a calculationtime which does not increase can be realized. In addition, since themultiplication device is operated in units of half clocks such as thefirst and second half clocks, the multiplication device is easilysynchronized with an external device, and is suitably used in aprecharge type adder.

In order to achieve the above object, the present invention provides asum of products calculation device in which a carry propagation adder isconnected to the output side of said accumulative addition resultholding circuit in said multiplication device through a carry saveadder, characterized in that,

at a third timing which is the first or second half of a clock andsucceeds the second timing after the clock switches,

an output from said accumulative addition result holding circuit andaddition data are added to each other by said carry save adder, and theaddition results in a carry save state are added to each other by saidcarry propagation adder to output a sum of products calculation result.

Therefore, according to the sum of products calculation device of thisinvention, a multiplication result in a carry save state of themultiplication device is temporarily added to the sum of products databy the carry save adder, and the results still in a carry state arefurther added to each other by the carry propagation adder. For thisreason, a time required for addition in sum of products calculation canbe shortened.

In order to achieve the above object, the present invention provides amultiplication device, comprising: a multiplicand holding circuit forholding multiplicand data; a multiplier holding circuit for holding thepredetermined number of bits from high-order bits of multiplier data; afirst selector for switching the predetermined number of bits fromlow-order bits of multiplier data to an output from said multiplierholding circuit according to turning from the first or second half of aclock to the second or first half of the clock; an encode circuit forencoding an output from said first selector; an intermediate resultholding circuit for holding intermediate result data; a second selectorfor switching an initial value to an output from said intermediateresult holding circuit according to turning from the first or secondhalf of the clock to the second or first half of the clock; a pluralityof partial product generation circuits for generating partial productson the basis of an output from said encode circuit and an output fromsaid multiplicand holding circuit; a plurality of accumulative additioncircuits for performing accumulative addition on the basis of an outputfrom said second selector or an output from a previous accumulativeaddition circuit and outputs from said partial product generationcircuits to generate the intermediate result data serving as anintermediate result of multiplication; an accumulative addition resultholding circuit for holding an output from the predetermined number ofsaid accumulative addition circuits and some of outputs from saidaccumulative addition circuits; and an output holding circuit forstoring some of the outputs from said accumulative addition circuits,characterized in that,

at a first timing which is the first or second half of the clock,

said firsts selector selects the predetermined number of bits from thelow-order bits of the multiplier data, said second selector selects theinitial value, each partial product generation circuit generates partialproducts on the basis of an encode result of said encode circuit and anoutput from said multiplicand holding circuit, each accumulativeaddition circuit adds an output from said second selector or an outputfrom a previous accumulative addition circuit to an output from saidpartial product Generation circuit, writes an output from thepredetermined number of said accumulative addition circuits in saidintermediate result holding circuit as the intermediate result data, andwrites the predetermined number of bits of the output from eachaccumulative addition circuit at a predetermined bit position of saidoutput holding circuit;

at a second timing which is the second or first half of a clock afterthe clock switches,

said first selector selects an output from said multiplier holdingcircuit, said second selector selects an output from said intermediateresult holding circuit, each partial product generation circuitgenerates partial products on the basis of an output from said encodecircuit and an output from said multiplicand holding circuit, eachaccumulative addition circuit adds an output from said second selectoror an output from a previous accumulative addition circuit to an outputfrom said partial product generation circuit, and writes the output fromsaid predetermined accumulative addition circuit and the predeterminednumber of bits of the output from each accumulative addition circuit insaid accumulative addition result holding circuit.

More specifically, according to the multiplication device of thisinvention, at the first timing which is the first or second half of theclock, each partial product generation circuit generates partialproducts on the basis of an encode result from the encode circuitobtained by encoding the predetermined number of bits from the low-orderbits of the multiplier data and an output from a multiplicand holdingcircuit, each accumulative addition circuit accumulatively adds theinitial value or an output from the previous accumulative additioncircuit to the partial products to perform calculation which is halfnecessary multiplication, writes the accumulation result from saidpredetermined accumulative addition circuit in the intermediate resultholding circuit as intermediate result data, and writes thepredetermined number of bits of an output from each accumulativeaddition circuit at a predetermined bit position of the output holdingcircuit. At the second timing at which the clock is switched to anotherone, each partial product generation circuit generates partial productson the basis of an output from said encode circuit and an output fromthe multiplicand holding circuit, each accumulative addition circuitaccumulatively adds an output from the intermediate result holdingcircuit or an output from the previous accumulative addition circuit toan output from the parietal product generation circuit to perform theremaining half the calculation, and writes the accumulative additionresult from the predetermined number of accumulation addition circuitsand the predetermined number of bits of an output from each accumulativeaddition circuit in the accumulative addition result holding circuit. Inthis manner, when the encode circuit is constituted by, e.g., Booth'salgorithm, the number of partial products generation circuits and thenumber of accumulative addition circuits can be made smaller than thosein the embodiment described first. For this reason, a time required foran accumulative addition process can be shortened.

In order to achieve the above object, the present invention provides asum of products calculation device in which a carry propagation adder isconnected to the output sides of said accumulative addition resultholding circuit and said output holding circuit in said multiplicationdevice through a carry save adder, characterized in that,

at a third timing which is the first or second half of a clock andsucceeds the second timing after the clock switches,

an output from said accumulative addition result holding circuit, anoutput from said output holding circuit, and addition data are added toeach other by said carry save adder, and the addition results in a carrysave state are added to each other by said carry propagation adder tooutput a sum of products calculation result.

Therefore, according to the sum of products calculation device of thisinvention, a multiplication result in a carry save state of themultiplier is temporarily added to the sum of products data by the carrysave adder, and the results still in a carry save state are furtheradded to each other by the carry propagation adder. For this reason, atime required for addition in sum of products calculation can beshortened.

According to a preferred embodiment of the present invention, saidencode circuit performs the encode on the basis of Booth's algorithm.

According to a preferred embodiment of the present invention,

each partial product generation circuit generates 0 times, 1 times, 2times, -1 times-1, and -2 times-1 the multiplicand data, one of 0 times,1 times, 2 times, -1 times-1, and -2 times-1 the multiplicand data isselected on the basis of select signals generated by performing theencode, each accumulative addition circuit adds 1 to the intermediateresult data when -1 times-1 or -2 times-1 the multiplicand data isselected.

According to this embodiment, a time loss and a hardware loss can besuppressed.

According to a preferred embodiment of the present invention, the sum ofproducts calculation device further comprises:

a sign holding circuit for holding a sign of a partial product in apredetermined stage;

in said first accumulative addition circuit, another full adder for signextension and two selectors for selectively outputting an input signaldepending on said first timing or the second timing to use twohigh-order bits of said accumulative addition circuit for signextension, said two selectors corresponding to the two bits,respectively; and

in said second accumulative addition circuit, two selectors forselectively outputting an input signal depending on the first timing orthe second timing to the two high-order bits of said accumulativeaddition circuit for sign extension, said two selectors corresponding tothe two bits, respectively.

According to this embodiment, sign extension can be reliably performed.

In order to achieve the above object, the present invention provides amultiplication device, comprising: a multiplicand holding circuit forholding multiplicand data; a multiplier holding circuit for holding thepredetermined number of bits from high-order bits of multiplier data; afirst selector for switching the predetermined number of bits fromlow-order bits of multiplier data to an output from said multiplierholding circuit according to turning from the first or second half of aclock to the second or first half of the clock; an encode circuit forencoding an output from said first selector; an encode result holdingcircuit for holding an encode result from said encode circuit each timea logical value of the clock changes to output the encode result; anintermediate result holding circuit for holding intermediate resultdata; a second selector for switching an initial value to an output fromsaid intermediate result holding circuit according to turning from thefirst or second half of the clock to the second or first half of theclock; a plurality of partial product generation circuits for generatingpartial products on the basis of an output from said encode resultholding circuit and an output from said multiple and holding circuit; aplurality of accumulative addition circuits for performing accumulativeaddition of the basis of an output from said second selector or anoutput from a previous accumulative addition circuit and outputs fromsaid partial product generation circuits to generate the intermediateresult data serving as an intermediate result of multiplication; anaccumulative addition result holding circuit for holding an output fromthe predetermined number of said accumulative addition circuits and someof outputs from said accumulative addition circuits, and an outputholding circuit for storing some of the outputs from said accumulativeaddition circuits, characterized in that,

at a first timing Which is the first or second half of the clock,

said first elector selects the predetermined number of bits from thelow-order bits of the multiplier data, and said encode circuit encodesan output from said first selector to write the encode result in saidencode result holding circuit,

at a second timing which is the second or first half of a clock afterthe clock switches,

said second selector selects the initial value, each partial productgeneration circuit generates partial products on the basis of an outputfrom said encode result holding circuit and an output from saidmultiplicand holding circuit, each accumulative addition circuit adds anoutput from said second selector or an output from a previousaccumulative addition circuit to an output from said partial productgeneration circuit, writes an output from the predetermined number ofaccumulative addition circuits in said intermediate result holdingcircuit as the intermediate result data, and writes the predeterminednumber of bits of the output from each accumulative addition circuit ata predetermined bit position of said output holding circuit, said firstselector selects an output from said multiplier holding circuit, andsaid encode circuit encodes an output from said first selector to writethe encode result in said encode result holding circuit;

at a third timing which is the second or first half of a clock andsucceeds the second timing after the clock switches,

said second selector selects an output from said intermediate resultholding circuit, each partial product generation circuit generatespartial products on the basis of an output from said encode resultholding circuit and an output from said muitiplicand holding circuit,each accumulative addition circuit adds an output from said secondselector or an output from a previous accumulative addition circuit toan output from said partial product generation circuit, and writes theoutput from said predetermined accumulative addition circuit and thepredetermined number of bits of the output from each accumulativeaddition circuit in said accumulative addition result holding circuit.

More specifically, according to the multiplication device of thisinvention, at the first timing which is the first or second half of theclock, the encode circuit encodes the predetermined number of bits fromlow-order bits of the multiplier data to write the encode result in theencode result holding circuit. At the second timing at which the clockis switched to another one, each partial product generation circuitgenerates partial products on the basis of an output from the encoderesult holding circuit held at the first timing and an output from themultiplicand holding circuit, each accumulative addition circuit addsthe initial value or an output from the previous accumulative additioncircuit to an output from the partial product generation circuit toperform calculation which is half necessary multiplication, writes theintermediate result data in the intermediate result holding circuit, andwrites the predetermined number of bits of an output from eachaccumulative addition circuit at a predetermined bit position of theoutput holding circuit, and the encode circuit encodes an output fromthe multiplier holding circuit to write the encode result in the encoderesult holding circuit. At the third timing at which the clock isswitched to another one, each partial product generation circuitgenerates partial products on the basis of an output from the encoderesult holding circuit held at the second timing and an output from themultiplicand holding circuit, each accumulative addition circuit adds anoutput from the intermediate result holding circuit held at the secondtiming or an output from the previous accumulative addition circuit toan output from the partial product generation circuit to perform theremaining half the calculation, and writes an output from thepredetermined number of accumulative addition circuits and thepredetermined number of bits of an output from each accumulativeaddition circuit in the accumulative addition result holding circuit. Inthis manner, a half clock is assigned as a passing time of the encodecircuit which is an overhead time in the multiplication device of theprevious present invention, and an operation can be performed in unitsof half clocks. Although a calculation time is prolonged by a halfcycle, times required to processes each performed in a half cycle arealmost equal to each other. For this reason, a clock frequency forcontrolling a calculation device can be made high.

In order to achieve the above object, the present invention provides asum of products calculation device in which a carry propagation adder isconnected to the output sides of said accumulative addition resultholding circuit and said output holding circuit in said multiplicationdevice through a carry save adder, characterized in that,

at a fourth timing which is the first or second half of a clock andsucceeds the third timing after the clock switches,

an output from said accumulative addition result holding circuit, anoutput from said output holding circuit, and addition data are added toeach other by said carry save adder, and the addition results in a carrysave state are added to each other by said carry propagation adder tooutput a sum of products calculation result.

Therefore, according to the sum of products calculation device of thisinvention, a multiplication result in a carry save state of themultiplier is temporarily added to the sum of products data by the carrysave adder, and the results still in a carry save state are furtheradded to each other by the carry propagation adder. For this reason, atime required for addition in sum of products calculation can beshortened.

According to a preferred embodiment of the present invention, saidencode circuit performs the encode on the basis of Booth's algorithm.

According to a preferred embodiment of the present invention,

each partial product generation circuit generates 0 times, 1 times, 2times, -1 times-1, and -2 times-1 the multiplicand data, one of 0 times,1 times, 2 times, -1 times-1, and -2 times-1 the multiplicand data isselected on the basis of select signals generated by performing theencode, each accumulative addition circuit adds 1 to the intermediateresult data when -1 times-1 or -2 times-1 the multiplicand data isselected.

According to this embodiment, a time loss and a hardware loss can besuppressed.

According to a preferred embodiment of the present invention, the sum ofproducts calculation device further comprises:

a sign holding circuit for holding a sign of a partial product in apredetermined stage;

in said first accumulative addition circuit, another full adder for signextension and two selectors for selectively outputting an input signaldepending on said first timing or the second timing to use twohigh-order bits of said accumulative addition circuit for signextension, said two selectors corresponding to the two bits,respectively; and

in said second accumulative addition circuit, two selectors forselectively outputting an input signal depending on the first timing orthe second timing to the two high-order bits of said accumulativeaddition circuit for sign extension, said two selectors corresponding tothe two bits, respectively.

According to this embodiment, sign extension can be reliably performed.

The nature, principle and utility of the invention will become moreapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a view showing the arrangement of a conventionalmultiplication device using a carry save adder scheme;

FIGS. 2 is view showing truth table of a full adder;

FIG. 3 is a view showing the arrangement of a conventional sum ofproducts calculation device using a carry save adder scheme;

FIG. 4 is a view showing the arrangement of a conventionalmultiplication device using a repeat addition scheme;

FIG. 5 is a view s owing the entire arrangement of a multiplicationdevice according to the first embodiment of the present invention;

FIG. 6 is a view showing the arrangement of each multiplication array inthe first embodiment;

FIG. 7 is a view for explaining the multiplication operation of themultiplication device according to the first embodiment;

FIG. 8 is a view showing the entire arrangement of a multiplicationdevice according to the second embodiment of the present invention;

FIG. 9 is a view showing the arrangement of a multiplication array on ahigh-order bit side in the second embodiment;

FIG. 10 is a view the arrangement of a multiplication array on alow-order bit side in the second embodiment;

FIG. 11 is a schematic view showing the arrangement of the third toeighth stages of the multiplication array in the second embodiment;

FIG. 12 is a view for explaining the multiplication operation of themultiplication device according to the second embodiment;

FIG. 13 is a view showing the entire arrangement of a multiplicationdevice according to the third embodiment of the present invention;

FIG. 14 is a circuit diagram of a double edge trigger latch circuit;

FIG. 15 is a flow chart showing the operation of the double edge triggerlatch circuit in FIG. 14;

FIG. 16 is a view for explaining the multiplication operation of themultiplication device according to the third embodiment; and

FIG. 17 is a view showing the entire arrangement of a sum of productscalculation device according to the fourth embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below withreference to the accompanying drawings.

FIG. 5 is a view showing the entire arrangement of a multiplicationdevice according to the first embodiment of the present invention.

This multiplication device has a function of performing multiplicationof 32 bits×32 bits, and comprises a 32-bit latch circuit 1 through whichthe 32 bits of a multiplicand pass at "H" level of a clock and whichholds the 32 bits of the multiplicand at "L" level of the clock, a16-bit latch circuit 2 through which the 16 high-order bits of the 32bits of a multiplier pass at "H" level of the clock and which holds the16 high-order bits at "L" level of the clock, and a 63-bit latch circuit3 through which intermediate result data (kept in a carry save form)output from the last stage of a multiplication array 6 (to be describedlater) passes at "H" level of the clock and which holds the intermediateresult data at "L" level.

The multiplication device also comprises a first selector 4 forperforming a switching operation between 16 low-order bits of amuitiplier and an output from the latch circuit 2 at "H"/"L" level ofthe clock, and a second selector 5 for performing a switching operationbetween ALL0 data (initial value) in which all 63 bits are 0 data and anoutput from the latch circuit 3 at "H"/"L" level of the clock. The firstand second selectors 4 and 5 and the output side of the latch circuit 1are connected to 16-stage multiplication array 6.

Each stage of the multiplication array 6 comprises, as shown in FIG. 6,a partial product generation circuit 6a constituted by AND gates of 32bits and an accumulative addition circuit 6b constituted by full addersof 32 bits. Sixteen circuits each having this arrangement are connectedto each other in the same connection method as that shown in FIG. 1,thereby constituting the multiplication array 6.

In this case, outputs from the latch circuit 1 and the latch circuit 2are set to be A<31:0> and B<15:0>, respectively. Of outputs (outputsfrom the accumulative addition circuits 6b) from the stages of themultiplication array 6, a carry output is set to be CO<31:0>, and a sumoutput is set to be SO<31:0>. In particular, a carry output CO<31:0>from the last stage of the multiplication array 6 Is set to beFCO<31:0>, a sum output SO<31:1> from the last stage is set to beFCO<30:0>, and a sum output from the least significant bit of each stageof the multiplication array 6 is set to be Z<15:0> (an output from theith stage is set to be Z<i-1>).

The latch circuit 3 outputs CC<31:0> and CS<30:0> corresponding to theFCO<31:0> and FSO<30:0> which are intermediate result data output fromthe last stage of the multiplication array 6. In addition, the selector4 outputs D<15:0>, and the second selector 5 outputs EC<31:0>corresponding to CC<31:0> or ALL0 data, and outputs ES<30:0>corresponding to CS<30:0> or ALL0 data.

A register (F/F) 7 and latch circuits 8 and 9 are connected to theoutput side of the multiplication array 6. The register 7 is a 16-bitregister for storing, in synchronism with rising of the clock CLK,Z<15:0> output from the least significant bit of the accumulativeaddition circuit 6b of each stage of the multiplication array 6. Likethe register 7, the latch circuit 8 is 16-bit latch circuit for holdingZ<15:0>, and is set in a through state at "L" level of the clock CLK andin a hold state at "H" level of the clock CLK. The latch circuit 9 holdsthe outputs SO<30:0> and FCO<31:0> from the last stage of themultiplication array 6, and is set in a through state at "L" level ofthe clock CLK and in a hold state at "H" level of the clock CLK. Anadder 10 for finally adding multiplication results in a carry save formto each other is connected to the output side of the latch circuit 9.

Note that an output from the register 7 is denoted by G<15:0>, and anoutput from the latch circuit 8 is denoted by H<15:0>. Of outputs fromthe latch circuit 9, an output corresponding to a carry output from thelast stage of the multiplication array 6 is denoted by OC<31:0>, and anoutput corresponding to a sum output from the last stage of themultiplication array 6 is denoted by OS<30:0>. An output from the adder10 is denoted by I<31:0>. An output from a multiplication deviceconstituted by the outputs G<15:0>, H<15:0>, and I<31:0> is denoted byOUT<63:0>.

The arrangement and function of the multiplication array 6 will bedescribed below.

As described above, each stage of the multiplication array 6 isconstituted by the partial product generation circuit 6a and theaccumulative addition circuit 6b. As shown in FIG. 6, input data a and band an output from the AND gate constituting each bit of the partialproduct generation circuit 6a are supplied to the full adderconstituting each bit of the accumulative addition circuit 6b. Note thatb<31>=0 is established. Each of output A<31:0> from the latch circuit 1is supplied to each of one input terminal of each AND gate of thepartial product generation circuit 6a, one bit of output D<15:0> fromthe selector 4 is commonly supplied to each of the other input terminalof the AND gates of the partial product generation circuit 6a.

In this case, each the input data a and b has 32-bit width<31:0>. Theoutput EC<31:0> from the selector 5 is supplied as input data a for thefirst stage, and the output ES<30:0> from the selector 5 is supplied asinput data b for the first stage.

Each stage of the multiplication array 6 causes the partial productgeneration circuit 6a to generate partial products on the basis of allthe bits of the output A<31:0> from the latch circuit 1 and one bit ofthe output D<15:0> from the selector 4, addition between the generatedpartial products and the input data a and b is performed by theaccumulative addition circuit 6b, thereby generating a carry outputCO<31:0> and a sum output SO<31:0>. Note that the truth table of eachfull adder constituting the accumulative addition circuit 6b is obtainedsuch that the input data a and b and the output from the partial productgeneration circuit 6a are caused to correspond to the inputs A, B, and Cof the truth table in FIG. 2, and the outputs CO and SO are caused tocorrespond to CO and Z of the truth table in FIG. 2.

The multiplication array 6 and its 16-stage connection will be describedbelow. In the first stage of the multiplication array 6, input datab<31>=0 is satisfied, and the above operation is performed to obtain anaddition result (D<0> of outputs from the selector 4 is supplied). A sumoutput SO<0> is externally output as Z<0>, the remaining sum outputSO<31:1> is output as input data b<30:0> for the second stage, and thecarry output CO<31:0> is output as input data a<31:0> for the secondstage.

In the second stage of the multiplication array 6, the above operationis performed in the same manner as described above to obtain an additionresult (D<1> of outputs from the selector 4 is supplied). A sum outputSO<0> is externally output as Z<1>, the remaining sum output SO<31:1> isoutput as input data b<30:0> for the third stage, and the carry outputCO<31:0> is output as input data a<31:0> for the third stage.

Assume that each of the stages following the third stage of themultiplication array 6 is the ith stage (i<16). In this case, the sameoperation as in the second stage is performed to obtain an additionresult (D<i-1> of outputs from the selector 4 is supplied). A sum outputSO<0> from the ith stage is externally output as Z<i-1>, the remainingsum output SO<31:1> is output as input data b<30:0> for the (i+1)thstage, and the carry output CO<31:0> is output as input data a<31:0> forthe (i+1)th stage. The sum output SO<0> of outputs from the last stage(16th stage) is externally output as Z<15>, and the remaining sum outputSO<31:1> and carry output CO<31:0> are externally output without anychange.

The multiplication operation of the multiplication device of thisembodiment arranged as described above will be described below withreference to FIG. 7.

(A) Operation in First Half 1 of Clock in E stage

As shown in FIG. 7, in the first half 1 ("H" level) of the clock CLK inE stage, the moment a multiplicand is written in the latch circuit 1,the 16 high-order bits of a multiplier are written in the latch circuit2. The selector 4 selects the 16 low-order bits of the multiplier. Inthis case, the 16 low-order bits of the multiplier are supplied to oneinput terminal of each AND gate of each of the 1st to 16th partial,product generation circuits 6a of the multiplication array 6 as anoutput D<15:0> from the selector 4 in order from <0> to <15>.

At this time, the latch circuit 1 is in a through state. For thisreason, the output A<31:0> serving as a multiplicand is supplied to theother input terminal of each AND gate of each partial product generationcircuit 6a of the multiplication array 6. In this manner, each stage ofthe multiplication array 6 generates partial products. On the otherhand, since the selector 5 selects ALL0 data, 0s are supplied as all theinput data a<31:0> and b<30:0> of the first stage of the multiplicationarray 6.

Accumulative addition is performed by using these data, therebyobtaining the Z<15:0> and the sum output FSO<30:0> and carry outputFCO<31:0> from the last stage. The outputs FCO<31:0> and FSO<30:0> fromthe last stage of the multiplication array 6 are written in only thelatch circuit 3, the output Z<15:0> is written in only the register 7because the latch circuit 8 is in a hold state.

(B) Operation in Second Half 2 of Clock in E stage

In the second half 2 (at "L" level) of the clock CLK in E stage, thelatch circuit 1 and the latch circuit 2 hold the values written in thefirst half 1 of the clock CLK, and the selector 4 selects an output (16high-order bits of a multiplier) from the latch circuit 2. In this case,the 16 high-order bits of the multiplier are supplied to one inputterminal of each AND gate of each of the 1st to 16th partial productgeneration circuits 6a of the multiplication array 6 as an outputD<15:0> from the selector 4 in order from <0> to <15>.

The multiplicand A<31 0> held by the latch circuit 1 is supplied to theother input terminal of each AND gate of each of the partial productgeneration circuits 6a of the multiplication array 6. In this manner,each stage of the multiplication array 6 generates partial products.

The latch circuit 3 holds a value written in the first half 1 of theclock CLK, and the selector 5 selects the outputs CC<31:0> and CS<30:0>from the latch circuit 3. As a result, EC<31:0> is supplied as the inputdata a<31:0> for the first stage of the multiplication array 6, andES<30:0> is supplied as the input data b<30:0> for the first stage.

Accumulative addition is performed by using these data, the outputZ<15:0> from the multiplication array 6 is written in only the latchcircuit 8, and the outputs FCO<31:0> and FSO<30:0> from the last stageof the multiplication array 6 are written in only the latch circuit 9.

(C) Operation in First Half 3 of Clock in M stage

In the first half 3 (at "H" level) in M stage next to E stage, theoutput G<15:0> from the register 7 is directly used as a final outputOUT<15:0>, and the output H<15:0> from the latch circuit 8 is directlyused as a final output OUT<31:16>. The outputs OS<30:0> and OC<31:0>from the latch circuit 9 are finally added to each other by the adder 10to generate I<31:0>, and I<31:0> is directly output as a final outputOUT<63:32>.

As described above, according to this embodiment, as shown in FIG. 7, avalue passes through the 16 stages of the multiplication array 6 in thefirst half 1 of the clock CLK to perform half necessary multiplication,and the obtained intermediate result is stored in the latch circuit 3.In the second half 2 of the clock CLK, calculation between the heldintermediate result and a result obtained by causing a value to passthrough the remaining 16 stages of the multiplication array 6 isperformed. In the first half 3 of the next clock CLK, the calculationresult is added to the result output from the multiplication array 6,and the addition result is output.

When the above series of operations are performed, the multiplicationarray can be repeatedly used in units of half clocks such that themultiplication array 6 is divided by two. For this reason, amultiplication device having the same performance as that of themultiplication device shown in FIG. 1 can be obtained by a hardwareamount half that of the multiplication device in FIG. 1. In addition,since the multiplication array is divided in units of half clocks, themultiplication array can be easily synchronized with an external circuitand can also be used in a precharge adder.

FIG. 8 is a view showing the entire arrangement of a multiplicationdevice according to the second embodiment of the present invention.

The multiplication device of this embodiment is a multiplication devicefor performing multiplication (multiplication with sign) of 32 bits×32bits by using Booth's algorithm. Since only partial products which are1/2 the partial products which are used in the first embodiment arerequired to be generated when Booth's algorithm is used, an 8-stagemultiplication array can be used in place of the 16-stage array in thefirst embodiment. Therefore, a time for an accumulation addition processcan be shortened.

As shown in FIG. 8, the multiplication device of this embodimentcomprises a 32-bit latch circuit 21 through which the 32 bits of amultiplicand pass at "H" level of a clock and which holds the 32 bits ofthe multiplicand at "L" level of the clock, a 17-bit latch circuit 22through which the 17 high-order bits of the 32 bits of a multiplier passat "H" level of the clock and which holds the 17 high-order bits at "L"level of the clock, and a 62-bit latch circuit 23 through whichintermediate result data output from the last stage of a multiplicationarray 27 (to be described later) passes at "H" level of the clock andwhich holds the intermediate result data at "L" level.

The multiplication device also comprises a selector 24 for performing aswitching operation between "0"+16 low-order bits of a multiplier and anoutput from the latch circuit 2 at "H"/"L" level of the clock, and aselector 25 for performing a switching operation between ALL0 data(initial value) in which all 62 bits are 0 data and an output from thelatch circuit 23 at "H"/"L" level of the clock.

A Booth's encoder 26 is arranged on the output side of the selector 24.An 8-stage multiplication array 27 is connected to the output sides ofthe latch circuit 21, the selector 25, and the Booth's encoder 26. TheBooth's encoder 26 encodes 17-bit input data according to secondaryBooth's algorithm to generate a control signal K for partial productgeneration.

Each stage of the multiplication array 27 is constituted by a partialproduct Generation circuit and an accumulative addition circuit (to bedescribed later). The partial product Generation circuit Generates 0times, 1 times, 2 times, -1 times-1, and -2 times-1 a multiplicand, andselects one of these values on the basis of the control signal K fromthe Booth's encoder 26. The accumulative addition circuit is constitutedby full adders (33 bits) which receives an output from the partialproduct generation circuit, an accumulative addition result up to this,and -1 and -2 times data for correcting a partial product. Note that theBooth's encoder 26 and the multiplication array 27 will be describedlater.

A 1-bit latch circuit 28 for holding a sign is connected to themultiplication array 27. This latch circuit 28 is a holding circuit inwhich the sign of a partial product generated in the eighth stage of themultiplication array 27 is held in the first half of the clock CLK, andthe held data is used to extend the sign in the second half of the clockCLK. The latch circuit 28 is set in a through state at "H" level of theclock CLK and in a hold state at "L" level of the clock CLK.

In this case, outputs from the latch circuit 21 and the latch circuit 22are denoted by A<31:0> and B<16:0>, respectively. A carry output fromeach stage of the multiplication array 27 is denoted by CO<32:0>, and asum output is denoted by SO<32:0>. In particular, a carry outputCO<32:2> from the last stage of the multiplication array 27 is denotedby FCO<30:0>, and a sum output SO<31:1> from the last stage is denotedby FCO<30:0>. In addition, outputs SO<1:0> and CO<1:0> of the 2low-order bits of each stage of the multiplication array 27 are denotedby ZSO and ZCO, respectively, the outputs ZSO and ZCO are used as theoutputs from the multiplication array 27.

The latch circuit 23 outputs CC<30:0> and CS<30:0> corresponding to theFCO<30:0> and FSO<30:0> which are intermediate result data output fromthe last stage of the multiplication array 27. The selector 24 outputsD<16:0>, and the selector 25 outputs EC<30:0> corresponding to CC<30:0>or ALL0 data, and outputs ES<30:0> corresponding to CS<30:0> or ALL0data.

A register (F/F) 29 and latch circuits 30 and 31 are connected to theoutput side of the multiplication array 27. The register 29 is a 32-bitregister for storing, in synchronism with rising of a clock CLK,ZCO<15:0> and ZSO<15:0> output from each stage of the multiplicationarray 27, and outputs from the register 29 corresponding to ZCO<15:0>and ZSO<15:0> are denoted by GC<15:0> and GS<15:0>, respectively. Thelatch circuit 30 is a 32-bit latch circuit for holding ZCO<15:6> andZSO<15:0> like the register 29, and is set in a through state at "L"level of the clock CLK and in a hold state at "H" level of the clockCLK. Outputs from the latch circuit 30 corresponding to ZCO<15:0> andZSO<15:0> are denoted by HC<15:0> and HS<15:0>, respectively.

The latch circuit 31 holds the outputs FSO<30:0> and FCO<30:0> from thelast stage of the multiplication array 27, and is set in a through stateat "L" level of the clock CLK and in a hold state at "H" level of theclock CLK. Outputs from the latch circuit 31 corresponding to FSO<30:0>and FCO<30:0> are denoted by OS<30:0> and OC<30:0>, respectively.

An adder 32 is connected to the output sides of the F/F 29 and the latchcircuits 30 and 31. The adder 32 finally adds the carry outputs and sumoutputs of each bit of a multiplication result set in a carry save formto output OUT<63:0> as an output from the multiplication device.

The Booth's encoder 26 and the multiplication array 27 which arecharacteristic parts in this embodiment will be described below. TheBooth's encoder 26 encodes an output from the selector 24 according toBooth's algorithm as described above. In this case, encode using Booth'salgorithm will be briefly described below.

A product Z between a multiplicand X and a multiplier Y is expressed asZ=X*Y. When the multiplier Y is expressed by 2's complement, themultiplier Y is expressed by equation (1): ##EQU1## When n is an evennumber, and a numerical portion is divided into even-number bits andodd-number bits, equation (2) is obtained: ##EQU2## Furthermore, theodd-number portion can be transformed as expressed by equation (3):##EQU3## A sign portion can be transformed as expressed by equation (4):##EQU4## For this reason, the multiplier Y can be expressed by equation(5): ##EQU5## In this case, when i=2j, equation (6) is established:##EQU6## Therefore, the product Z can be expressed by equation (7):##EQU7## (Supervised by Takuo Sugano, Edited by Testuya Iizuka, "Designof CMOS Very High Speed LSI", Baifukan (1989) pp. 224-226).

As is apparent from equation (7), when Booth's algorithm is used,partial products can be generated by a 5-input selector having 3adjacent bits of the multiplier Y as a selection condition and a selectsignal for controlling the selector.

Therefore, the Booth's encoder 26 has a function of generating 5 (5bits) select signals K for controlling the 5-input selector to eachstage of the multiplication array 27. That is, 5 signals K are presentfor each stage because the signals K are used for the 5-input selector.Since the multiplication array 27 is constituted by 8 stages, 40 selectsignal K<39:0> are used.

The arrangement and function of the multiplication array 27 will bedescribed below with reference to FIGS. 9, 10, and 11. Note that FIG. 9is a view showing the high-order bit arrangement of the multiplicationarray, 27 in FIG. 8, FIG. 10 is a view showing the low-order bitarrangement of the multiplication array 27, and FIG. 11 is a schematicview showing the arrangement of the third to eighth stages of themultiplication array 27.

As shown in FIGS. 9 to 11, each stage of the multiplication array 27 isconstituted by a partial product generation circuit 27a for generatingpartial products and an accumulative addition circuit 27b for performingaccumulative addition on the basis of the partial products generated bythe partial product generation circuit 27a.

The partial product generation circuit 27a must be originallyconstituted by a means for generating partial products required forBooth's algorithm described above, i.e., (-2, -1, 0, 1, and 2) times amultiplicand, and a selector for selecting one of these values on thebasis of the 5 select signals K supplied from the Booth's encoder 26.However, since "1" must be added to -2 times and -1 times themultiplicand after each bit is inverted in generation, a time loss And ahardware loss are large.

Therefore, -2 times and -1 times the multiplicand are only inverted inthe partial product generation circuit 27a of each stage in thisembodiment, "1" is added to the values in the following accumulativeaddition. More specifically, the partial product generation circuit 27aof each stage generates 2 times, 1 times, 0 times, -2 times-1, and -1times-1 the multiplicand, and one of these values is selected on the 5select signals K from the Booth's encoder 26. At this time, when ±2times the multiplicand is obtained, 32-bit data changes into 33-bitdata. For this reason, the selector of the partial product generationcircuit 27a of each stage outputs all data as 33-bit data c<32:0> (seeFIG. 11).

The accumulative addition circuit 27b of each stage is constituted byfull adders of 33 bits because the 33-bit partial products are generatedby the partial product generation circuit 27a. In correspondence withmultiplication using Booth's algorithm, sign extension must be performedin the most significant bit of the accumulative addition circuit 27b.

More specifically, sign extension performed when partial products areadded to each other according to Booth's algorithm is performed in thefollowing manner. For example, for descriptive convenience,multiplication of 8-bit numbers is exemplified. In this case, when thesigns of the partial products are represented by SGN1, SGN3, SGN5, andSGN7 in order from the low-order bit side, equation (8) is obtained:##EQU8## (Supervised by Takuo Sugano, Edited by Susumu Kayama "Very HighSpeed Digital Device Series, Very High Speed MOS Device", Baifukan(1986) p. 296).

Therefore, sign extension is performed such that signals and circuitsrequired to satisfy an equation obtained by extending equation (8) for32-bit data are additionally used.

In this embodiment, although multiplication is originally performed atonce, multiplication is separately performed in the first and secondhalves of the clock CLK. In accordance with the multiplication, in eachof the 1st and 9th stages of the multiplication array used inmultiplication performed at once, different extension operations must beperformed the same hardware. For this reason, a necessary hardware isselected by selectors using the clock CLK as a selection signal. Theseselectors are shown in FIG. 9 as selectors 27c and 27d on the high-orderbit side of the first stage of the multiplication array 27 and selectors27e and 27f on the high-order bit side of the second stage.

In addition, between the last stage (8th stage) and the first stage (1ststage) of the multiplication array 27, the signs of partial productsgenerated by the 8th stage must be held for sign extension. For thisreason, the latch circuit 28 having the same operation as that of thelatch circuit (intermediate result holding circuit) 23 is arranged, thesigns of the partial products generated by the 8th stage are written inthe latch circuit 28 in the first half of the clock, and the signs isinput in the second half of the clock to the accumulative additioncircuit 27b of the first stage as an input for sign extension.

More specifically, in the first stage of each accumulative additioncircuit 27b of the multiplication array 27, as shown in FIG. 9, inaddition to the full adders of 33 bits, a full adder 27g for signextension is also arranged. The full adder 27g and full adders (a<32>and b<32:31> in FIG. 9) of the two high-order bits (32nd and 33rd bits)perform sign extension, and the result is given to the second stage. Inthe accumulative addition circuit 27b of the second stage, as shown inFIG. 9, sign extension is performed by the full adders of the twohigh-order bits (32nd and 33rd bits) using the selectors 27e and 27f,and the result is given to the third stage. In each of the stagesfollowing the third stage, shown in FIG. 9, sign extension is performedby the full adders of the two high-order bits (32nd and 33rd bits), andthe result is given to the next stage, thereby inputting an output C<32>from the partial product generation circuit 27a of the last stage (8thstage) to the latch circuit 28.

The accumulative addition circuit 27b of each stage adds theaccumulative addition result of the previous stage to partial productsgenerated by the partial product generation circuit 27a of this stage(to be described later). In this case, however, when -2 times or -1times a multiplicand is selected as a partial product on the basis of aBooth's encode result (select signal K), "1" is input to a<0>(corresponding to carry in) serving as one of inputs of the full adderof the least significant bit of the accumulative addition circuit 27b,values other than -2 times or -1 times the multiplicand are selected,"0" is input. This switching operation is performed by a selector 27harranged in each stage as shown in FIG. 10.

In the accumulative addition circuit 27b of the first stage, outputsES<30:0> and EC<30:0> from the selector 25 are added to the partialproducts c<32:0> generated by the partial product generation circuit 27aof the first stage. Of the obtained outputs CO<32:0> and SO<32:0> fromthe first stage, outputs CO<1:0> and SO<1:0> are externally output asZCO<1:0> and ZSO<1:0>, and the remaining outputs CO<32:2> and SO<32:2>are supplied to the accumulative addition circuit 27b of the secondstage as input data a<31:1> and b<30:0>.

In the accumulative addition circuit 27b of the second stage, theintermediate result from the first stage is accumulatively added to thepartial products generated by the partial product generation circuit 27aof the second stage. Of the obtained outputs CO<32:0> and SO<32:0> fromthe second stage, outputs CO<1:0> and SO<1:0> are externally output asZCO<3:2> and ZSO<3:2>, and the remaining outputs CO<32:2> and SO<32:2>are supplied to the accumulative addition circuit 27b of the third stageas input data a<31:1> and b<30:0>.

In the accumulative addition circuit 27b of each of the stages followingthe third stage, as in the connection between the first and secondstages, the ith stage is exemplified. In this case, outputs SO<1:0> andCO<1:0> from the ith stage are externally output as ZSO<2i-1:2i-2> andZCO<2I-1:2i-2>, and the remaining outputs SO<32:2> and CO<32:2> areoutput as input data b<30:0> and a<31:1> of the (i+1)th stage,respectively. Outputs SO<1:0> and CO<1:0> from the 8th stage serving asthe last stage are output as ZSO<15:14> and ZCO<15:14>, respectively,and the remaining outputs SO<32:2> and CO<32:2> are externally outputwithout any change.

The multiplication operation of the multiplication device according tothis embodiment arranged as described above will be described below withreference to FIG. 12.

(A) Operation in First Half 1 of Clock in E stage

As shown in FIG. 12, in the first half 1 ("H" level) of the clock CLK inE stage, the moment the 32 bits of a multiplicand are written in thelatch circuit 21, the 17 high-order bits of a multiplier are written inthe latch circuit 22. The selector 24 selects 17-bit data obtained byadding "0" to the low order of the 16 low-order bits of the multiplier.Since the multiplier has 32 bits, the 16th bit from the leastsignificant bit of the multiplier is stored in the latch circuit 22 andsupplied to the Booth's encoder 26 even in the first half of the clockCLK.

When the selector 24 selects the low-order side of the multiplier, anoutput D<16:0> from the selector 24 is encoded by the Booth's encoder26, and is supplied to the partial product generation circuit 27a ofeach stage of the multiplication array 27 as a select signal K. At thistime, since the latch circuit 21 is in a through state, an outputA<31:0> (serving as a multiplicand) from the latch circuit 21 issupplied to the partial product generation circuit 27a of each stage ofthe multiplication array 27. In this manner, partial products (0 times,1 times, 2 times, -1 times -1, and -2 times -1) are generated by thepartial product generation circuit 27a of each stage of themultiplication array 27.

Since the selector 25 selects ALL0 data (all of them are set to be "0")for EC<30:0> and ES<30:0>, "0"" is supplied as all the input dataa<31:1> and b<30:0> of the accumulative addition circuit 27b of thefirst stage. Data (1/0) for correcting partial product generation isinput as input data a<0> of the accumulative addition circuit 27b ofeach stage. Sign extension data are input as a<32> and b<32:31>.

When accumulative addition is performed by using these data, ZCO<15:0>and ZOS<15:0> are output from the multiplication array 27, and FSO<30:0>and FCO<30:0> are output from the last stage. Of these outputs, theoutputs FCO<30:0> and FSO<30:0> are written in only the latch circuit23, and the outputs ZCO<15:0> and ZSO<15:0> are written in only theregister 29 because the latch circuit 30 is set in a hold state.

The signs of the partial products generated by the last stage of themultiplication array 27 are stored in the latch circuit 28.

(B) Operation in Second Half 2 of Clock in E stage

In the second half 2 (at "L" level) of the clock CLK in E stage, thelatch circuit 21 and the latch circuit 22 hold the values written in thefirst half 1 of the clock CLK, and the selector 24 selects an output (17high-order bits of a multiplier) from the latch circuit 22. In thiscase, an output D<16:0> from the selector 24 is encoded by the Booth'sencoder 26 and supplied to the partial product generation circuit 27a ofeach stage of the multiplication array 27 as a select signal K. At thistime, an output A<31:0> (multiplicand) from the latch circuit 21 issupplied to the partial product generation circuit 27a of each stage ofthe multiplication array 27. Therefore, a partial product (one of 0times, 1 times, 2 times, -1 times -1, and -2 times -1 the multiplicand)is generated.

Since the selector 25 selects CC<30:0> and CS<30:0> as EC<30:0> andES<30:0>, respectively, CC<30:0> and CS<30:0> are supplied as input dataa<31:1> and b<30:0> of the accumulative addition circuit 27b of thefirst stage, respectively. Data (1/0) for correcting partial productgeneration is input as input data a<0> of the accumulative additioncircuit 27b of each state. Sign extension data are input as a<32> andb<32:31>.

When accumulative addition is performed by using these data, ZCO<15:0>and ZOS<15:0> are output from the multiplication array 27, and FSO<30:0>and FCO<30:0> are output from the last stage. Of these outputs, theoutputs FCO<30:0> and FSO<30:0> are written in the latch circuit 31, andthe outputs ZCO<15:0> and ZSO<15:0> are written in the latch circuit 30.

(C) Operation in First Half 3 of Clock in M stage

In the first half 3 (at "H" level) of the clock CLK in M stage next to Estage, the adder 32 performs the following final addition to obtain anoutput OUT<63:0>

    {OC<30:0>, HC<15:0>, GC<15:0>, 0}+{0, OS<30:0>, HS<15:0>, GS<15:0>}

As described above, according to this embodiment, Booth's encode for the16 low-order bits of the multiplier is performed in the first half 1 ofthe clock CLK as shown in FIG. 12. The resultant value passes throughthe 8 stage of the multiplication array to perform half necessarymultiplication, and the intermediate result is stored in the latchcircuit 23. In the second half 2 of the clock CLK, the 17 high-orderbits of the multiplier is encoded. Calculation and accumulative additionbetween the encode result and the stored intermediate result areperformed. In the first half 3 of the clock CLK, output results from themultiplication array 27 are added to each other, and the addition resultis output.

With the above series of operations, the number of multiplication arraystages through which a value passes can be made 1/2 the number ofmultiplication array stages in the first embodiment, a time required topass through the multiplication array can be shortened.

FIG. 13 is a view showing the entire arrangement of a multiplicationdevice according to the third embodiment of the present invention. Thesame reference numerals as in FIG. 8 denote the same parts in FIG. 13.

In the second embodiment, although high-speed multiplication can beperformed by reducing the number of stages of the multiplication array,the Booth's encoder 26 requires a predetermined time for encoding. Forthis reason, according to this embodiment, in consideration of thispoint, a double edge trigger latch circuit 41 is inserted between theBooth's encoder 26 and the multiplication array 27. In this case,although a calculation time increases by a half cycle, required timesfor processes performed in half cycles are almost equal to each other.Therefore, a multiplication device which can be controlled by a clockhaving a frequency higher than that of the second embodiment can beprovided.

More specifically, the multiplication device of this embodiment isobtained in the following manner. That is, in the multiplication deviceof the second embodiment shown in FIG. 8, the double edge trigger latchcircuit 41 having an output which changes at an edge of a clock CLK isinserted between the Booth's encoder 26 and the multiplication array 27,a 32-bit latch circuit 42 is inserted between the latch circuit 21 andthe multiplication array 27. A latch circuit 23a, a selector 25a, alatch circuit 28a, a register 29a, a latch circuit 30a, and a latchcircuit 31a which respectively have functions different from the latchcircuit 23, the selector 25, the latch circuit 28, the register 29, thelatch circuit 30, and the latch circuit 31 are arranged in place ofthese parts. Assume that an output from the double edge trigger latchcircuit 41 is L<39:0> and that an output from the latch circuit 42 isM<31:0>. In this case, the outputs L<39:0> and M<31:0> are supplied tothe multiplication array 27 in place of K<39:0> and A<39:0>. Theremaining arrangement of the third embodiment is the same as that of thesecond embodiment.

The latch circuit 23a, the selector 25a, the latch circuit 28a, theregister 29a, the latch circuit 30a, and the latch circuit 31a aredifferent from those of the second embodiment in the following points.The latch circuit 23a is set in a through state at "L" level of theclock CLK and in a hold state at "H" level of the clock CLK. Theselector 25a performs a switching operation between an output from thelatch circuit 23a and ALL0 data at "H" level/"L" level. The latchcircuit 28a is set in a through state at "L" level of the clock CLK andin a hold state at "H" level of the clock CLK, and the register 29a isset in a write state at "L" level and in an output state at "H" level.The latch circuit 30a is set in a through state at "H" level of theclock CLK and in a hold state at "L" level of the clock CLK, and thelatch circuit 31a is set in a through state at "H" level of the clockCLK and in a hold state at "L" level of the clock CLK. Note that theinput data and bit arrangements of the latch circuits 23a, 28a, 30a, and31a and the register 29a are the same as those of the latch circuits 23,28, 30, and 31 and the register 29 in the second embodiment.

FIG. 14 is a circuit diagram showing the arrangement of the double edgetrigger latch circuit 41, and FIG. 15 is a time chart showing theoperation of the double edge trigger latch circuit 41.

The double edge trigger latch circuit 41 of this embodiment isconstituted by a pair of latch circuits 41a and 41b which respectivelyoperate in opposite phases, and a selector 41c for selecting one ofoutputs from the latch circuits 41a and 41b on the basis of the value ofthe clock CLK.

In its operation, as shown in FIG. 15, when the clock CLK is invertedwhen an input is data d1, an output from the double edge trigger latchcircuit 41 changes into data d1. At this time, even if the input changesinto data d2, the output is held as data d1. Thereafter, when the clockCLK is inverted, the output changes into the data d2. As in the abovecase, even if the input changes, the output is held as data d2. That is,an operation in which an input is held and output is performed each timethe clock CLK changes. The latch circuit 42 is set in a through state at"L" level of the clock CLK and in a hold state at "H" level of the clockCLK.

The multiplication operation of the multiplication device of thisembodiment arranged as described above will be described below withreference to FIG. 16.

(A) Operation in First Half 1 of Clock in E stage

As shown in FIG. 16, in the first half 1 ("H" level) of the clock CLK inE stage, the moment the 32 bits of a multiplicand are written in thelatch circuit 21, the 17 high-order bits of a multiplier are written inthe latch circuit 22. The selector 24 selects 17-bit data obtained byadding "0" to the low order of the 16 low-order bits of the multiplier.

When the selector 24 selects the low-order side of the multiplier, anoutput D<16:0> from the selector 24 is encoded by the Booth's encoder26, and the encode result is stored in the double edge trigger latchcircuit 41.

(B) Operation in Second Half 2 of Clock in E stage

In the second half 2 (at "L" level) of the clock CLK in E stage, anoutput A<31:0> from the latch circuit 21 is stored in the latch circuit42, an output M<31:0> from the latch circuit 42 is supplied to thepartial product generation circuit 27a of each stage of themultiplication array 27. An encode result from the Booth's encoder 26stored in the first half i of the clock CLK is supplied by the doubleedge trigger latch circuit 41 to the partial product generation circuit27a of each stage of the multiplication array 27. In this manner, apartial product is generated by the partial product generation circuit27a of each stage of the multiplication array 27.

Since the selector 25a selects ALL0 data for EC<30:0> and ES<30:0>, "0"is supplied as all the input data a<31:1> and b<30:0> of theaccumulative addition circuit 27b of the first stage. Data (1/0) forcorrecting partial product generation is input as input data a<0> of theaccumulative addition circuit 27b of each stage. Sign extension data areinput as a<32> and b<32:31>.

When accumulative addition is performed by using these data, ZCO<15:0>,ZOS<15:0>, FSO<30:0>, and FCO<30:0> are output from the multiplicationarray 27. Of these outputs, the outputs FCO<30:0> and FSO<30:0> arewritten in the latch circuit 23a, and the outputs ZCO<15:0> andZSO<15:0> are written in the register 29a. The sign of a partial productgenerated by the last stage of the multiplication array 27 is stored inthe latch circuit 28a.

The selector 24 selects an output from the latch circuit 22, and anoutput D<16:0> from the selector 24 is encoded by the Booth's encoder26. The encode result K is stored in the double edge trigger latchcircuit 41.

(C) Operation in Second Half 3 of Clock in E stage

In the second half 3 (at "H" level) of the clock CLK in E stage, thelatch circuit 42 holds the value written in the second half 2 of theclock CLK, and an output M<31:0> from the latch circuit 42 is suppliedto the partial product generation circuit 27a of each stage of themultiplication array 27. The encode result stored in the second half 2of the clock CLK is supplied from the double edge trigger latch circuit41 to the partial product generation circuit 27a of each stage of themultiplication array 27. In this manner, a partial product is generatedby the partial product generation circuit 27a of each stage of themultiplication array 27.

Since the selector 25a selects an output from the latch circuit 23a,CC<30:0> and CS<30:0> are supplied as the input data a<31:0> and b<30:0>of the accumulative addition circuit 27b of the first stage. Data (1/0)for correcting partial product generation is input as input data a<0> ofthe accumulative addition circuit 27b of each stage. Sign extension dataare input as a<32> and b<32:31>.

When accumulative addition is performed by using these data, ZCO<15:0>,ZOS<15:0>, FSO<30:0>, and FCO<30:0> are output from the multiplicationarray 27. Of these outputs, the outputs FCO<30:0> and FSO<30:0> arewritten in the latch circuit 31a, and the outputs ZCO<15:0> andZSO<15:0> are written in the register 30a.

(D) Operation in Second Half 3 of Clock in M stage

In the second half 4 (at "L" level) in M stage next to E stage, theadder 32 performs the following final addition to obtain an outputOUT<63:0>

    {OC<30:0>, HC<15:0>, GC<15:0>, 0}+{0, OS<30:0>, HS<15:0>, GS<15:0>}

As described above, according to this embodiment, Booth's encode for the16 low-order bits of the multiplier is performed in the first half 1 ofthe clock CLK as shown in FIG. 16. The resultant value is stored in thedouble edge trigger latch circuit 41. In the second half 2 of the clock,the Booth's encode result is output from the double edge trigger latchcircuit 41, and the resultant value passes through the 8 stages of themultiplication array to perform half necessary multiplication. Thisoutput is stored in the latch circuit 23a as intermediate result data.Furthermore, Booth's encode is performed to the 17 high-order bits ofthe multiplier while the value passes through the multiplication array27, and the encode result is stored in the double edge trigger latchcircuit 41. In the first half 3 of the clock, calculation andaccumulative addition between the stored intermediate result data and avalue which passes through the remaining 8 stages of the multiplicationarray 27 is performed. In the second half 4 of the next clock CLK,output results from the multiplication array 27 are added to each other,and an output OUT from the multiplication device is obtained. In thismanner, the series of operations are performed.

In the second embodiment, although the number of stages of themultiplication array 27 is reduced, the passing time of the Booth'sencoder 26 is an overhead time. In contrast to this, in the thirdembodiment, when a half clock is assigned as an encode time of theBooth's encoder 26, and the double edge trigger latch circuit 41 isused, times required for processes performed in half cycles are almostequal to each other. For this reason, the frequency of the clock CLK canbe made higher than that of the second embodiment.

FIG. 17 is a view showing the entire arrangement of a sum of productscalculation device according to the fourth embodiment of the presentinvention. The same reference numerals as in FIG. 13 denote the sameparts in FIG. 17.

In this embodiment, on the basis of the multiplication device of thethird embodiment, a sum of products calculation device capable of sum ofproducts calculation (with sign) at a high speed of 32 bits×32 bits+64bits is constituted. More specifically, in the multiplication device ofthe third embodiment shown in FIG. 13, a 64-bit carry save adder 51 isarranged on the output sides of the F/F 29a and the latch circuits 30aand 31a, and an adder 32a with CLA for performing addition for sum ofproducts in a carry save form is arranged, as an adder connected to theoutput side of the carry save adder 51, in place of the adder 32described above. The remaining arrangement is the same as that of thethird embodiment.

In this case, in addition to an output from the F/F 29a and outputs fromthe latch circuits 30a and 31a, addition data Q<63:0> is supplied to theinput terminal of the carry save adder 51. A carry signal NC<63:0> andan addition result NS<63:0> are output from the carry save adder 51 asoutput signals.

In the sum of products calculation device of this embodiment having theabove arrangement, the same operations as the operations (A) to (C) inthe first half 1 of the first clock to the first half 3 of the secondclock in the multiplication device of the third embodiment areperformed. However, the sum of products calculation device performs anoperation different from the operation (D) in the second half 4 of thesecond clock in the multiplication device of the third embodiment.

More specifically, in the second half 4 of the second clock of thisembodiment, the carry save adder 51 finally adds the outputs from thelatch circuit 31a, the latch circuit 30a, and the register 29a, and, atthe same time, the addition data Q<63:0> is added to the final additionresult. That is, the carry save adder 51 has three input terminals, and{OC, HC, GC, 0}, {0, OS, HS, GS}, and the addition data Q<63:0> aresupplied to the first, second, and third input terminals of the carrysave adder 51, respectively.

The carry signal NC<63:0> and addition result NS<63:0> output from thecarry save adder 51 are added to each other by the adder 32a with CAL asdescribed below:

    {NC<63:0>, 0}+{0, NS<63:0>}

thereby obtaining an addition result OUT<63:0>.

When sum of products calculation is to be performed by using themultiplication device described in the third embodiment, after amultiplication result is obtained by the multiplication device shown inFIG. 13, addition must be performed. However, addition using the adderwith CLA requires a long time. In consideration of this point, accordingto the fourth embodiment, a multiplication result in a carry save formand addition data are temporarily added to each other by the carry saveadder 51, and the results are added to each other by the adder 32a withCAL. For this reason, an addition time in the sum of productscalculation can be shortened. In this embodiment, although a circuitscale smaller than that of the prior art can be obtained, a calculationtime is not prolonged.

Although the fourth embodiment describes that sum of productscalculation is performed by using the multiplication device described inthe third embodiment, sum of products calculation can also be performedby the multiplication device described in the first or secondembodiment.

It should be understood that many modifications and adaptations of theinvention will become apparent to those skilled in the art and it isintended to encompass such obvious modifications and changes in thescope of the claims appended hereto.

What is claimed is:
 1. A multiplication device, comprising:amultiplicand holding circuit for holding multiplicand data; a multiplierholding circuit for holding predetermined number of bits from high-orderbits of multiplier data; a first selector for switching predeterminednumber of bits from low-order bits of multiplier data to an output fromsaid multiplier holding circuit according to turning from the first orsecond half of a clock to the second or first half of the clock; anintermediate result holding circuit for holding intermediate resultdata; a second selector for switching an initial value to an output fromsaid intermediate result holding circuit according to turning from thefirst or second half of the clock into the second or first half of theclock; a plurality of partial product generation circuits for generatingpartial products on the basis of an output from said first selector andan output from said multiplicand holding circuit; a plurality ofaccumulative addition circuits for performing accumulative addition onthe basis of an output from said second selector or an output from aprevious accumulative addition circuit and outputs from said partialproduct generation circuits to generate the intermediate result dataserving as an intermediate result of multiplication; an accumulativeaddition result holding circuit for holding an output from thepredetermined number of said accumulative addition circuits and some ofoutput from each of said accumulative addition circuits; and an outputholding circuit for storing some of the output from each of saidaccumulative addition circuits, characterized in that, at a first timingwhich is the first or second half of the clock, said first selectorselects predetermined number of bits from the low-order bits of themultiplier data, said second selector selects the initial valued, eachpartial product generation circuit generates partial products on thebasis of one bit of an output from said first selector and an outputfrom each bit of said multiplicand holding circuit, each accumulativeaddition circuit adds an output from said second selector or an outputfrom a previous accumulative addition circuit to an output from saidpartial product generation circuit, writes an output from thepredetermined number of said accumulative addition circuits in saidintermediate result holding circuit as the intermediate result data, andwrites the predetermined number of bits of the output from eachaccumulative addition circuit at a predetermined bit position of saidoutput holding circuit; at a second timing which is the second or firsthalf of a clock after the clock switches, said first selector selects anoutput from said multiplier holding circuit, said second selectorselects an output from said intermediate result holding circuit, eachpartial product generation circuit generates partial products on thebasis of one bit of the output from said first selector and an outputfrom each bit of said multiplicand holding circuit, each accumulativeaddition circuit adds an output from said second selector or an outputfrom a previous accumulative addition circuit to an output from saidpartial product generation circuit, and writes the output from thepredetermined number of said accumulative addition circuits and thepredetermined number of bits of the output from each accumulativeaddition circuit in said accumulative addition result holding circuit.2. A sum of products calculation device in which a carry propagationadder is connected to the output side of said accumulative additionresult holding circuit in said multiplication device according to claim1 through a carry save adder, characterized in that,at a third timingwhich is the first or second half of a clock and succeeds the secondtiming after the clock switches, an output from said accumulativeaddition result holding circuit and addition data are added to eachother by said carry save adder, and the addition results in a carry savestate are added to each other by said carry propagation adder to outputa sum of products calculation result.
 3. A multiplication device,comprising:a multiplicand holding circuit for holding multiplicand data;a multiplier holding circuit for holding a predetermined number of bitsfrom high-order bits of multiplier data; a first selector for switchinga predetermined number of bits from low-order bits of multiplier data toan output from said multiplier holding circuit according to turning fromthe first or second half of a clock to the second or first half of theclock; an encode circuit for encoding an output from said firstselector; an intermediate result holding circuit for holdingintermediate result data; a second selector for switching an initialvalue to an output from said intermediate result holding circuitaccording to turning from the first or second half of a clock to thesecond or first half of the clock; a plurality of partial productgeneration circuits for generating partial products on the basis of anoutput from said encode circuit and an output from said multiplicandholding circuit; a plurality of accumulative addition circuits forperforming accumulative addition on the basis of an output from saidsecond selector or an output from a previous accumulative additioncircuit and outputs from said partial product generation circuits togenerate the intermediate result data serving as an intermediate resultof multiplication; an accumulative addition result holding circuit forholding an output from the predetermined number of said accumulativeaddition circuits and some of output from each of said accumulativeaddition circuits; and an output holding circuit for storing some of theoutput from each of said accumulative addition circuits; characterizedin that, at a first timing which is the first or second half of theclock, said first selector selects a predetermined number of bits fromthe low-order bits of the multiplier data, said second selector selectsthe initial value, each partial product generation circuit generatespartial products on the basis of an encode result of said encode circuitand an output from said multiplicand holding circuit, each accumulativeaddition circuit adds an output from said second selector or an outputfrom a previous accumulative addition circuit to an output from saidpartial product generation circuit, writes an output from saidpredetermined number of accumulative addition circuits in saidintermediate result holding circuit as the intermediate result data, andwrites the predetermined number of bits of the output from eachaccumulative addition circuit at a predetermined bit position of saidoutput holding circuit; at a second timing which is the second or firsthalf of a clock after the clock switches, said first selector selects anoutput from said multiplier holding circuit, said second selectorselects an output from said intermediate result holding circuit, eachpartial product generation circuit generates partial products on thebasis of an output from said encode circuit and an output from saidmultiplicand holding circuit, each accumulative addition circuit adds anoutput from said second selector or an output from a previousaccumulative addition circuit to an output from said partial productgeneration circuit, and writes the output from the predetermined numberof said accumulative addition circuits and the predetermined number ofbits of the output from each accumulative addition circuit in saidaccumulative addition result holding circuit.
 4. A multiplication deviceaccording to claim 3, characterized in that said encode circuit performsthe encode on the basis of Booth's algorithm.
 5. A multiplication deviceaccording to claim 4, characterized in that,each partial productgeneration circuit generates 0 times, 1 times, 2 times, -1 times-1, and-2 times-1 the multiplicand data, one of 0 times, 1 times, 2 times, -1times-1, and -2 times-1 the multiplicand data is selected on the basisof select signals generated by performing the encode, each accumulativeaddition circuit adds 1 to the intermediate result data when -1 times-1or -2 times-1 the multiplicand data is selected.
 6. A multiplicationdevice according to claim 4, characterized by further comprising:a signholding circuit for holding a sign of a partial product in apredetermined stage; in said first accumulative addition circuit,another full adder for sign extension and two selectors for selectivelyoutputting an input signal depending on said first timing or the secondtiming to use two high-order bits of said accumulative addition circuitfor sign extension, said two selectors corresponding to the two bits,respectively; and in said second accumulative addition circuit, twoselectors for selectively outputting an input signal depending on thefirst timing or the second timing to the two high-order bits of saidaccumulative addition circuit for sign extension, said two selectorscorresponding to the two bits, respectively.
 7. A sum of productscalculation device in which a carry propagation adder is connected tothe output sides of said accumulative addition result holding circuitand said output holding circuit in said multiplication device accordingto claim 3 through a carry save adder, characterized in that,at a thirdtiming which is the first or second half of a clock and succeeds thesecond timing after the clock switches, an output from said accumulativeaddition result holding circuit, an output from said output holdingcircuit, and addition data are added to each other by said carry saveadder, and the addition results in a carry save state are added to eachother by said carry propagation adder to output a sum of productscalculation result.
 8. A multiplication device according to claim 7,characterized in that said encode circuit performs the encode on thebasis of Booth's algorithm.
 9. A multiplication device according toclaim 8, characterized in that,each partial product generation circuitgenerates 0 times, 1 times, 2 times, -1 times-1, and -2 times-1 themultiplicand data, one of 0 times, 1 times, 2 times, -1 times-1, and -2times-1 the multiplicand data is selected on the basis of select signalsgenerated by performing the encode, each accumulative addition circuitadds 1 to the intermediate result data when -1 times-1 or -2 times-1 themultiplicand data is selected.
 10. A multiplication device according toclaim 8, characterized by further comprising:a sign holding circuit forholding a sign of a partial product in a predetermined stage; in saidfirst accumulative addition circuit, another full adder for signextension and two selectors for selectively outputting an input signaldepending on said first timing or the second timing to use twohigh-order bits of said accumulative addition circuit for signextension, said two selectors corresponding to the two bits,respectively; and in said second accumulative addition circuit, twoselectors for selectively outputting an input signal depending on thefirst timing or the second timing to the two high-order bits of saidaccumulative addition circuit for sign extension, said two selectorscorresponding to the two bits, respectively.
 11. A multiplicationdevice, comprising:a multiplicand holding circuit for holdingmultiplicand data; a multiplier holding circuit for holding apredetermined number of bits from high-order bits of multiplier data; afirst selector for switching a predetermined number of bits fromlow-order bits of multiplier data to an output from said multiplierholding circuit according to turning from the first or second half of aclock to the second or first half of the clock; an encode circuit forencoding an output from said first selector; an encode result holdingcircuit for holding an encode result from said encode circuit each timea logical value of the clock changes to output the encode result; anintermediate result holding circuit for holding intermediate resultdata; a second selector for switching an initial value to an output fromsaid intermediate result holding circuit according to turning from thefirst or second half of the clock to the second or first half of theclock; a plurality of partial product generation circuits for generatingpartial products on the basis of an output from said encode resultholding circuit and an output from said multiplicand holding circuit; aplurality of accumulative addition circuits for performing accumulativeaddition on the basis of an output from said second selector or anoutput from a previous accumulative addition circuit and outputs fromsaid partial product generation circuits to generate the intermediateresult data serving as an intermediate result of multiplication; anaccumulative addition result holding circuit for holding an output fromthe predetermined number of said accumulative addition circuits and someof outputs from said accumulative addition circuits; and an outputholding circuit for storing some of the outputs from said accumulativeaddition circuits, characterized in that, at a first timing which is thefirst or second half of the clock, said first selector selects thepredetermined number of bits from the low-order bits of the multiplierdata, and said encode circuit encodes an output from said first selectorto write the encode result in said encode result holding circuit, at asecond timing which is the second or first half of a clock after theclock switches, said second selector selects the initial value, eachpartial product generation circuit generates partial products on thebasis of an output from said encode result holding circuit and an outputfrom said multiplicand holding circuit, each accumulative additioncircuit adds an output from said second selector or an output from aprevious accumulative addition circuit to an output from said partialproduct generation circuit, writes an output from the predeterminednumber of said accumulative addition circuit in said intermediate resultholding circuit as the intermediate result data, and writes thepredetermined number of bits of the output from each accumulativeaddition circuit at a predetermined bit position of said output holdingcircuit, said first selector selects an output from said multiplierholding circuit, and said encode circuit encodes an output from saidfirst selector to write the encode result in said encode result holdingcircuit; at a third timing which is the second or first half of a clockand succeeds the second timing after the clock switches, said secondselector selects an output from said intermediate result holdingcircuit, each partial product generation circuit generates partialproducts on the basis of an output from said encode result holdingcircuit and an output from said multiplicand holding circuit, eachaccumulative addition circuit adds an output from said second selectoror an output from a previous accumulative addition circuit to an outputfrom said partial product generation circuit, and writes the output fromthe predetermined number of said accumulative addition circuit and thepredetermined number of bits of the output from each accumulativeaddition circuit in said accumulative addition result holding circuit.12. A multiplication device according to claim 11, characterized in thatsaid encode circuit performs the encode on the basis of Booth'salgorithm.
 13. A multiplication device according to claim 12,characterized in that,each partial product generation circuit generates0 times, 1 times, 2 times, -1 times-1, and -2 times-1 the multiplicanddata, one of 0 times, 1 times, 2 times, -1 times-1, and -2 times-1 themultiplicand data is selected on the basis of select signals generatedby performing the encode, each accumulative addition circuit adds 1 tothe intermediate result data when -1 times-1 or -2 times-1 themultiplicand data is selected.
 14. A multiplication device according toclaim 12, characterized by further comprising:a sign holding circuit forholding a sign of a partial product in a predetermined stage; in saidfirst accumulative addition circuit, another full adder for signextension and two selectors for selectively outputting an input signaldepending on said second timing or the third timing to use twohigh-order bits of said accumulative addition circuit for signextension, said two selectors corresponding to the two bits,respectively; and in said second accumulative addition circuit, twoselectors for selectively outputting an input signal depending on thesecond timing or the third timing to the two high-order bits of saidaccumulative addition circuit for sign extension, said two selectorscorresponding to the two bits, respectively.
 15. A sum of productscalculation device in which a carry propagation adder is connected tothe output sides of said accumulative addition result holding circuitand said output holding circuit in said multiplication device accordingto claim 11 through a carry save adder, characterized in that,at afourth timing which is the first or second half of a clock and succeedsthe third timing after the clock stitches, an output from saidaccumulative addition result holding circuit, an output from said outputholding circuit, and addition data are added to each other by said carrysave adder, and the addition results in a carry save state are added toeach other by said carry propagation adder to output a sum of productscalculation result.
 16. A multiplication device according to claim 15,characterized in that said encode circuit performs the encode on thebasis of Booth's algorithm.
 17. A multiplication device according toclaim 16, characterized in that,each partial product generation circuitgenerates 0 times, 1 times, 2 times, -1 times-1, and -2 times-1 themultiplicand data, one of 0 times, 1 times, 2 times, -1 times-1, and -2times-1 the multiplicand data is selected on the basis of select signalsgenerated by performing the encode, each accumulative addition circuitadds 1 to the intermediate result data when -1 times-1 or -2 times-1 themultiplicand data is selected.
 18. A multiplication device according toclaim 16, characterized by further comprising:a sign holding circuit forholding a sign of a partial product in a predetermined stage; in saidfirst accumulative addition circuit, another full adder for signextension and two selectors for selectively outputting an input signaldepending on said second timing or the third timing to use twohigh-order bits of said accumulative addition circuit for signextension, said two selectors corresponding to the two bits,respectively; andin said second accumulative addition circuit, twoselectors for selectively outputting an input signal depending on thesecond timing or the third timing to the two high-order bits of saidaccumulative addition circuit for sign extension, said two selectorscorresponding to the two bits, respectively.